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? semiconductor components industries, llc, 2013 february, 2013 ? rev. 10 1 publication order number: noil1sm0300a/d noil1sm0300a lupa300 cmos image sensor features ? 640(h) x 480(v) active pixels (vga resolution) ? 9.9 m x 9.9 m square pixels (based on the high-fill factor active pixel sensor technology of fillfactory (us patent no. 6,225,670 and others)). ? optical format: 1/2 optical inch ? pixel rate of 80 mhz ? frame rate: 250 fps at full resolution ? on-chip 10 bit adcs ? global shutter ? subsampling (y direction) ? serial pheripheral interface (spi) ? programmable read out direction (x and y) ? random programmable windowing ? power dissipation: 190 mw ? 48-pin lcc package ? these devices are pb ? free and are rohs compliant applications ? machine vision ? motion tracking overview this document describes the interfacing and driving of the lupa300 image sensor. the pixel size and resolution result in a 6.3 mm x 4.7 mm optical active area (1/2 inch). this vga-resolution cmos active pixel sensor features global shutter and a maximal frame rate of 250 fps in full resolution, where integration during readout is possible. the readout speed can be boosted by means of subsampling and windowed region of interest (roi) readout. high dynamic range scenes can be captured using the double and multiple slope functionality. user programmable row and column start/stop positions allow windowing. subsampling reduces resolution while maintaining the constant field of view and an increased frame rate. the programmable gain and offset amplifier maps the signal swing to the adc input range. a 10-bit adc converts the analog data to a 10-bit digital word stream. the sensor uses a 3-wire serial-parallel (spi) interface. it operates with a 3.3 v and 2.5 v power supply and requires only one master clock for operation up to 80 mhz pixel rate. it is housed in an 48-pin ceramic lcc package. the sensor is available in a monochrome version or bayer (rgb) patterned color filter array. this data sheet allows the user to develop a camera-system based on the described timing and interfacing. ordering information marketing part number description package noil1sm0300a-qdc mono with glass 48 pin lcc NOIL1SE0300A-QDC color micro lens with glass noil1sm0300a-wwc mono wafer sales wafer sales note: for more information, see ordering code information on page 27. http://onsemi.com figure 1. lupa300 package photo
noil1sm0300a http://onsemi.com 2 contents features 1 ..................................... applications 1 ................................. overview 1 .................................... ordering information 1 ......................... contents 2 .................................... specifications 3 ................................ absolute maximum ratings 3 ................... spectral response curve 4 ...................... photo ? voltaic response curve 4 ................. sensor architecture 5 ........................... pixel architecture 5 ........................... frame rate and windowing 6 ................... analog to digital converter 6 ................... programmable gain amplifiers 7 ................ operation and signaling 9 ...................... global shutter 11 .............................. non destructive readout (ndr) 11 ............... sequencer 12 ................................. data interface (spi) 16 ......................... timing and readout of the image sensor 17 ......... readout timing 20 ............................. startup timing 22 ............................. sequencer reset timing 22 ...................... pin list 23 ..................................... package drawing 25 ............................. mechanical package specification 26 .............. glass lid 27 .................................. handling precautions 27 ......................... limited warranty 27 ............................ return material authorization (rma) 27 ........... acceptance criteria specification 27 ............... ordering code information 27 .................... acronyms 28 ................................... glossary 29 .................................... appendix a: frequently asked questions 30 ........
noil1sm0300a http://onsemi.com 3 specifications general specifications parameter specifications pixel architecture 6 transistor pixel pixel size 9.9 m x 9.9 m resolution 640 (h) x 480 (v) subsampling subsampling is possible (only in the y-direction) sub-sampling pattern: y0y0y0y0 windowing (roi) randomly programmable roi read out. implemented as scanning of lines/ columns from an uploaded position read out direction read out direction can be reversed in x and y programmable gain range x1 to x16, in 16 steps using 4-bits programming programmable offset 256 steps (8 bit) digital output on ? chip 10 ? bit adcs at 80 msamples/s power dissipation 160 mw not including output load 190 mw with output load of 15 pf package type 48 pin lcc mass 1 g electro ? optical specifications parameter typical specifications optical format ? optical inch shutter type pipelined global shutter frame rate 250 fps fpn 2.5% rms p-p (min: 10%, max: 3.1%) prnu 2.5% rms, max: 3.1% conversion gain 34 uv/e - at output saturation charge 35.000 e - sensitivity 3200 v.m2/w.s 17 v/lux.s (180 lux = 1 w/m 2 ) peak qe * ff 45% dark current (at 21 c) 300 mv/s noise electrons 32e - s/n ratio 43 db parasitic sensitivity 1/5000 dynamic range 61 db extended dynamic range multiple slope (up to 90 db optical dy- namic range) mtf 60% table 1. recommended operating ratings (notes 1 and 2) ?????? ?????? symbol ??????????????????? ??????????????????? ???? ???? ???? ???? ???? ???? ?????? ?????? t j ??????????????????? ??????????????????? ???? ???? ? 40 ???? ???? ???? ???? c table 2. absolute maximum ratings (notes 2, 3 and 4) ?????? ?????? symbol ?????????????????? ?????????????????? ???? ???? ????? ????? ???? ???? ?????? ?????? v dd [5] ?????????????????? ?????????????????? ???? ???? ? 0.5 ????? ????? ???? ???? ?????? ?????? ?????????????????? ?????????????????? ???? ???? ? 30 ????? ????? ???? ???? c ?????? ?????? ?????????????????? ?????????????????? ???? ???? ? ????? ????? 85% at 85 c ???? ???? ?????? ?????? ?????????????????? ?????????????????? ? up ???????? ???????? ???? ???? ? a. refer to application note an52561. 4. the lupa300 does not have latchup protection. 5. v dd = v ddd = v dda (v ddd is supply to digital circuit, v dda to analog circuit).
noil1sm0300a http://onsemi.com 4 spectral response curve figure 2. spectral response of lupa300 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 400 wavelength (nm) response (a/w) 0.16 500 600 700 800 900 1000 photo ? voltaic response curve figure 3. photo ? voltaic response lupa300 0 0.2 0.4 0.6 0.8 1 1.2 0.00e+00 electrons output voltage (analog) 1.00e+04 2.00e+04 3.00e+04 4.00e+04 5.00e+04 6.00e+04 7.00e+04
noil1sm0300a http://onsemi.com 5 sensor architecture the floor plan of the architecture is shown in figure 4. the image core consists of a pixel array, an x- and y -addressing register, pixel array drivers, and column amplifiers. the image sensor of 640 x 480 pixels is read out in progressive scan. the architecture allows programmable addressing in the x-direction in steps of 8 pixels and in the y-direction in steps of 1 pixel. the starting point of the address is uploadable by means of the serial parallel interface (spi). the pgas amplify the signal from the column and add an offset so the signal fits in the input range of the adc. the four adcs then convert the signal to the digital domain. pixels are selected in a 4 * 1 kernel. every adc samples the signal from one of the 4 selected pixels. sampling frequency is 20 mhz. the digital outputs of the four adcs are multiplexed to one output bus operating at 80 mhz. figure 4. floor plan of the sensor pixel architecture the lupa300 is designed on the 6t pixel architecture. color filter the lupa300 can also be processed with a bayer rgb color pattern. pixel (0,0) has a red filter. figure 5. color filter arrangement on the pixels
noil1sm0300a http://onsemi.com 6 frame rate and windowing frame rate the frame rate depends on the input clock, the frame overhead t ime (fot) and the row overhead time (rot). the frame period is calculated as follows frame period = fot + nr. lines * (rot + nr. pixels * clock period) example: read out of the full resolution at nominal speed (80 mhz pixel rate = 12.5 ns, gran<1:0>=10): frame period = 7.8 s + (480 * (400 ns + 12.5 ns * 640) = 4.039 ms => 247.6 fps. in case the sensor operates in subsampling, the rot is enlarged with 8 clock periods. table 3. frame rate parameters parameter comment clarification fot frame overhead time 1200 clock periods for gran<1:0> = 11 624 clock periods for gran<1:0> = 10 336 clock periods for gran<1:0> = 01 192 clock periods for gran<1:0> = 00 rot row overhead time 48 clock periods for gran<1:0> = 11 32 clock periods for gran<1:0> = 10 24 clock periods for gran<1:0> = 01 20 clock periods for gran<1:0> = 00 nr. lines number of lines read out each frame nr. pixels number of pixels read out each line clock period 1/80 mhz = 12.5 ns windowing windowing is achieved by the spi interface. the starting point of the x- and y-address is uploadable, as well as the window size. the minimum step size in the x-direction is 8 pixels (only multiples of 8 can be chosen as start/stop addresses). the minimum step size in the y-direction is 1 line (every line can be addressed) in normal mode and 2 lines in subsampling mode. the window size in the x-direction is uploadable in register nb_of_pix. the window size in the y-direction is determined by the register ft_timer table 4. frame rate parameters parameter frame rate (fps) frame readout (us) comment 640 x 480 247.5 4038 640 x 240 488.3 2048 subsampling 256 x 256 1076 929 windowing analog to digital converter the sensor has four 10-bit pipelined adc on board. the adcs are nominally operating at 20 msamples/s. the input range of the adc is between 0.75 and 1.75v. the analog input signal is sampled at 2.1 ns delay from the rising edge of the adc clock. the digital output data appears at the output at 5.5 cycles later. this is at the 6th falling edge succeeding the sample moment. the data is delayed by 3.7 ns with respect to this falling edge. this is illustrated in figure 6. table 5. adc parameters parameter specification data rate 20 msamples/s input range 0.75 v ? 1.75 v quantization 10 bit dnl typ. < 0.3 lsb inl typ. < 0.7 lsb
noil1sm0300a http://onsemi.com 7 figure 6. adc timing clk_adc dummy 50ns 3.7ns 5.5 clock cycles adc_in d1 d2 d3 d4 d5 d6 d7 d8 d1 d2 d3 d4 adc_out <9:0> programmable gain amplifiers the programmable gain amplifiers have two functions: ? adding an offset to the signal to fit it into the range of the adc. this is controlled by the vblack and voffset spi settings. ? amplifying the signal after the offset is added. offset regulation the purpose of offset regulation is to bring the signal in the input range of the adc. after the column amplifiers, the signal from the pixels has a range from 0.1v (bright) to 1.3v (black). the input range of the adc is from 0.75v to 1.75v. the amount of offset added is controlled by two spi settings: vblack<7:0> and voffset<7:0>. the formula to add offset is: voutput = vsignal + (voffset - vblack) note that the fpn (fixed pattern noise) of the sensor causes a spread of about 100 mv on the dark level. to allow fpn correction during post processing of the image, this spread on the dark level needs to be covered by the input range of the adc. this is why the default settings of the spi are programmed to add an offset of 200 mv. this way the dark level goes from 1.3v to 1.5v and is the fpn information still converted by the adc. to match the adc range, it is recommended to program an offset of 340 mv. to program this offset, the voffset and vblack registers can be used. figure 7 illustrates the operation of the offset regulation with an example. the blue histogram is the histogram of the image taken after the column amplifiers. consider as an example that the device has a black level of 1.45v and a swing of 100 mv. with this swing, it fits in the input range of the adc, but a large part of the range of the adc is not used in this case. for this reason an offset is added first, to align the black level with the input range of the adc. in the first step, an offset of 200 mv is added with the default settings of vblack and voffset. this results in the red histogram with a average black level of 1.65v. this means that the spread on the black level falls completely inside the range of the adc. in a second step, the signal is amplified to use the full range of the adc. figure 7. offset regulation number of pixels volts 1.45v1.65v vadc_high 1.75v
noil1sm0300a http://onsemi.com 8 programmable gain the amplification inside the pga is controlled by three spi settings: the pga gain selection: 16 gain steps are selectable by means of the gain_pga<3:0> register. selection word 0000 corresponds with gain 1.32 and selection word 1111 corresponds with gain 15.5. table 6 gives the 16 gain settings. the unity gain selection of the pga is done by the unity_pga setting. if this bit is high, the gain_pga settings are ignored. the sel_uni setting is used to have more gain steps. if this bit is low, the signal is divided by two before entering the pga. gain_pga and unity_pga settings are applied afterwards. if the sel_uni bit is high, there is a unity feed through to the pga. this allows having a total gain range of 0.5 to 16 in 32 steps. the amplification in the pga is done around a pivoting point, set by vcal as illustrated in figure 8. the vcal<7:0> setting is used to apply the vcal voltage through an on chip dac figure 8. effect on histogram of pga (gain = 4) (vcal is the green line) number of pixels volts vcal figure 9 continues on the example in the section, offset regulation. the blue histogram is the histogram of the image after the column amplifiers. w ith offset regulation an offset of 200 mv is added to bring the signal in range of the adc. the black level of 1.45v is shifted to 1.65v. the red and blue histograms have a swing of 100 mv. this means the input range of the adc is not completely used. by amplifying the signal with a factor 10 by the pga, the full range of the adc can be used. in this example, vcal is set at 1.75v (the maximum input range of the adc) to make sure the spread on the black level is still inside the range of the adc after amplification. the result after amplification is the purple histogram. table 6. gain settings gain_pga<3.0> gain 0000 1.32 0001 1.56 0010 1.85 0011 2.18 0100 2.58 0101 3.05 0110 3.59 0111 4.22 1000 4.9 1001 5.84 1010 6.84 1011 8.02 1100 9.38 1101 11.2 1110 13.12 1111 15.38 figure 9. example of pga operation number of pixels volts 1.45v1.65v vcal 1.75v 0.75v
noil1sm0300a http://onsemi.com 9 operation and signaling power supplies every module on chip such as column amplifiers, output stages, digital modules, and drivers has its own power supply and ground. off chip the grounds can be combined, but not all power supplies may be combined. this results in several different power supplies, but this is required to reduce electrical cross-talk and to improve shielding, dynamic range, and output swing. on chip, the ground lines of every module are kept separate to improve shielding and electrical cross-talk between them. an overview of the supplies is given in table 7 and table 8. t able 8 summarizes the supplies realted to the pixel array signals, where table 7 summarizes the supplies related with all other modules. table 7. frame rate parameters name dc current peak current typ max description v dda 15.7 ma 50 ma 2.5 v 5% power supply analog readout module v ddd 6.7 ma 50 ma 2.5 v 2.5 v power supply digital modules v adc 32.7 ma 100 ma 2.5 v 5% power supply of adc circuitry v ddo 3.5 ma 100 ma 2.5 v 5% power supply output drivers table 8. overview of the power supplies related to pixel signals name dc current peak current min typ max description v pix 3 ma 100 ma 2.5 v power supply pixel array v res 1 a 10 ma 3.0 v 3.3 v 3.5 v power supply reset drivers v res_ds 1 a 10 ma 2.8 v power supply reset dual slope drivers v res_ts 1 a 10 ma 2.0 v power supply reset triple slope drivers v mem_h 1 a 1 a 3.0 v 3.3 v 3.5 v power supply for memory element in pixel gnd drivers 0 v ground of the pixel array drivers the maximum currents mentioned in table 7 and table 8 are peak currents. all power supplies should be able to deliver these currents except for vmem_l, which must be able to sink this current. note that no power supply filtering on chip is implemented and that noise on these power supplies can contribute immediately to the noise on the signal. the voltage supplies v pix, v dda and v adc are especially important to be noise free.
noil1sm0300a http://onsemi.com 10 biasing table 9 summarizes the biasing signals required to drive this image sensor. for optimization reasons of the biasing of the column amplifiers with respect to power dissipation, several biasing resistors are required. this optimization results in an increase of signal swing and dynamic range. table 9. overview of bias signals signal [1] comment related module dc ? level adc_bias connect with 10 k to v adc and decouple with 100n to gnd adc adc 693 mv precharge_bias connect with 68 k to v pix and decouple with 100 nf to gnd drivers pixel array precharge 567 mv bias_pga biasing of amplifier stage. connect with 110 k to v dda and de- couple with 100 nf to gnd a pga 650 mv bias_fast biasing of columns. connect with 42 k to v dda and decouple with 100 nf to gnd a column amplifiers 750 mv bias_slow biasing of columns. connect with 1.5 m to v dda and decouple with 100 nf to gnd a column amplifiers 450 mv bias_col biasing of imager core. connect with 500 k to v dda and decouple with 100 nf to gnd a column amplifiers 508 mv 1. each biasing signal determines the operation of a corresponding module in the sense that it controls speed and dissipation. digital signals depending on the operation mode (master or slave), the pixel array of the image sensor requires different digital control signals. the function of each of the signals is shown in table 10. table 10. overview of bias signals signal i/o comments line_valid digital output indicates when valid data is at the outputs. active high frame_valid digital output indicates when a valid frame is readout. active high int_time_3 digital i/o in master mode: output to indicate the triple slope integration time. in slave mode: input to control the triple slope integration time. active high int_time_2 digital i/o in master mode: output to indicate the dual slope integration time. in slave mode: input to control the dual slope integration time. active high int_time_1 digital i/o in master mode: output to indicate the integration time. in slave mode: input to control integration time. active high reset_n digital input sequencer reset. active low clk digital input readout clock (80 mhz), sine or square clock spi_enable digital input enable of the spi spi_clk digital input clock of the spi. (max. 20 mhz) spi_data digital i/o data line of the spi. bidirectional pin
noil1sm0300a http://onsemi.com 11 global shutter in a global shutter light integration takes place on all pixels in parallel, although subsequent readout is sequential. figure 10 shows the integration and read out sequence for the synchronous shutter. all pixels are light sensitive at the same period of time. the whole pixel core is reset simultaneously and after the integration time all pixel values are sampled together on the storage node inside each pixel. the pixel core is read out line by line after integration. note that the integration and read out cycle can occur in parallel or in sequential mode. figure 10. synchronous shutter operation time axis line number integration time burst readout time common reset common sample&hold flash could occur here non destructive readout (ndr) figure 11. principle of non destructive readout [1] time the sensor can also be read out in a non destructive way. after a pixel is initially reset, it can be read multiple times, without resetting. the initial reset level and all intermediate signals can be recorded. high light levels saturate the pixels quickly, but a useful signal is obtained from the early samples. for low light levels, one has to use the later or latest samples. essentially an active pixel array is read multiple times, and reset only once. the external system intelligence takes care of the interpretation of the data. table 11 summarizes the advantages and disadvantages of non destructive readout. note 1:this mode can be activated by setting the ndr spi register. the ndr spi register must only be changed during fot. the nd r bit should be set high during the first frame overhead time after the pixel array is reset; the ndr bit must be set low during the last frame overhead time before the pixel array is being reset.
noil1sm0300a http://onsemi.com 12 table 11. advantages and disadvantages of non destructive readout advantages disadvantages low noise because it is a true cds. system memory required to record the reset level and the interme- diate samples. high sensitivity because the conversion capacitance is kept rather low. requires multiples readings of each pixel, thus higher data throughput. high dynamic range because the results includes signal for short and long integrations times. requires system level digital calculations. sequencer the sequencer generates the complete internal timing of the pixel array and the readout. the timing can be controlled by the user through the spi register settings. the sequencer operates on the same clock as the adcs. this is a division by 4 of the input clock. table 12 shows a list of the internal registers with a short description. in the next section, the registers are explained in more detail. table 12. internal registers address bits name description 0 (0000) 10:0 sequencer default <10:0>: 00000101001 1 mastermode 1: master mode; 0: slave mode 1 ss 1: ss in y; 0: no subsampling 2 gran clock granularity 1 enable_analog_out 1: enabled; 0: disabled 1 calib_line 1: line calibration; 0 frame calibration 1 res2_en 1: enable ds; 0: disable ds 1 res3_en 1: enable ts; 0: disable ts 1 reverse_x 1: readout in reverse x direction 0: readout in normal x direction 1 reverse_y 1: readout in reverse y direction 0: readout in normal y direction 1 ndr 1: enable non destructive readout 0: disable non destructive readout 1 (0001) 7:0 start_x start pointer x readout default <7:0>: 00000000 2 (0010) 8:0 start_y start pointer y readout default <8:0>: 000000000 3 (0011) 7:0 nb_pix number of kernels to read out (4 pixel kernel) default <7:0>: 10100000 4 (0100) 11:0 res1_length length of reset pulse (in number of lines) default <11:0>: 000000000010 5 (0101) 11:0 res2_timer position of reset ds pulse in number of lines default <11:0>: 000000000000 6 (0110) 11:0 res3_timer position of reset ts pulse in number of lines default <11:0>: 000000000000 7(0111) 11:0 ft_timer position of frame transfer in number of lines default <11:0>: 000111100001 8 (1000) 7:0 vcal dac input for vcal default <7:0>: 01001010
noil1sm0300a http://onsemi.com 13 table 12. internal registers address description name bits 9 (1001) 7:0 vblack dac input for vblack default <7:0>: 01101011 10 (1010) 7:0 voffset dac input for voffset default <7:0>: 01010101 11 (1011) 11:0 ana_in_adc activate analog adc input default <11:0>: 000011110000 4 sel_test_path selection of analog test path 4 sel_path selection of normal analog path 4 bypass_mux bypass of digital 4 to 1 mux 12 (1100) 11:0 pga_setting pga settings default <11:0>: 1 11110110000 4 gain_pga gain settings pga 1 unity_pga pga unity amplification 1 sel_uni preamplification of 0.5 (0: enabled) 1 enable_analog_in activate analog input 4 enable_adc put separate adcs in standby 1 sel_calib_fast select fast calibration of pga 13 (1101) 11:0 calib_adc <11:0> calibration word of the adcs default: calib_adc<11:0>:10101101 1111 calib_adc<23:12>:011011011011 calib_adc<32:24>:000011011011 14 (1110) 11:0 calib_adc <23:12> 15 (1111) 8:0 calib_adc <32:24> detailed description of the internal registers the registers should only be changed during fot (when frame valid is low). these registers should only be changed during reset_n is low: ? mastermode register ? granularity register sequencer register <10:0> the sequencer register is an 11 bit wide register that controls all of the sequencer settings. it contains several ?sub-registers?. mastermode (1 bit) this bit controls the selection of mastermode/slavemode. the sequencer can operate in two modes: master mode and slave mode. in master mode all the internal timing is controlled by the sequencer, based on the spi settings. in slave mode the integration timing is directly controlled over three pins, the readout timing is still controlled by the sequencer. 1: master mode (default) 0: slave mode subsampling (1bit) this bit enables/disables the subsampling mode. subsampling is only possible in y direction and follows this pattern: ? read one, skip one: y0y0y0y0 ? by default, the subsampling mode is disabled. clock granularity (2 bits) the system clock (80 mhz) is divided several times on chip. the clock, that drives the ?snapshot? or synchronous shutter sequencer, can be programmed using the granularity register. the value of this register depends on the speed of your system clock. 11: > 80 mhz 10: 40-80 mhz (default) 01: 20-40 mhz 00: < 20 mhz enable analog out (1 bit) this bit enables/disables the analog output amplifier. 1: enabled 0: disabled (default) calib_line (1bit) this bit sets the calibration method of the pga. dif ferent calibration modes can be set, at the beginning of the frame and for every subsequent line that is read. 1: calibration is done every line (default) 0: calibration is done every frame (less row fixed pattern noise)
noil1sm0300a http://onsemi.com 14 res2_enable (1bit) this bit enables/disables the dual slope mode of the device. 1: dual slope is enabled (configured according to the res2_timer register) 0: dual slope is disabled (res2_timer register is ignored) - default res3_enable (1bit) this bit enables/disables the triple slope mode of the device. 1: triple slope is enabled (configured according to the res3_timer register) 0: triple slope is disabled (res3_timer register is ignored) - default reverse_x (1bit) the readout direction in x can be reversed by setting this bit through the spi. 1: read direction is reversed (from right to left) 0: normal read direction (from left to right) - default reverse_y (1bit) the readout direction in y can be reversed by setting this bit through the spi. 1: read direction is reversed (from bottom to top) 0: normal read direction (from top to bottom) - default ndr (1 bit) this bit enables the non destructive readout mode if desired. 1: ndr enables 0: ndr disables (default) start_x register <7:0> this register sets the start position of the readout in x direction. in this direction, there are 80 (from 0 to 79) possible start positions (8 pixels are addressed at the same time in one clock cycle). remember that if you put start_x to 0, pixel 0 is being read out. example: if you set 23 in the start_x register readout only starts from pixel 184 (8x23). start_y register <8:0> this register sets the start position of the readout in y direction. in this direction, there are 480 (from 0 to 479) possible start positions. this means that the start position in y direction can be set on a line by line basis. nb_pix <7:0> this register sets the number of pixels to read out. the number of pixels to be read out is expressed as a number of kernels in this register (4 pixels per kernel). this means that there are 160 possible values for the register (from 1 to 160). example: if you set 37 in the nb_pix register, 148 (37 x 4) pixels are read out. res1_length <11:0> this register sets the length of the reset pulse (how long it remains high). this length is expressed as a number of lines (res1_length - 1). the minimum and default value of this register is 2. the actual time the reset is high is calculated with the following formula: reset high = (res1_length-1) * (rot + nr. pixels * clock period) res2_timer <11:0> this register defines the position of the additional reset pulse to enable the dual slope capability. this is also defined as a number of lines-1. the actual time on which the additional reset is given is calculated with the following formula: ds high = (res2_timer-1) * (rot + nr. pixels * clock period) res3_timer <11:0> this register defines the position of the additional reset pulse to enable the triple slope capability. this is also defined as a number of lines - 1. the actual time on which the additional reset is given is calculated with the following formula: ts high = (res3_timer-1) * (rot + nr. pixels * clock period) ft_timer <11:0> this register sets the position of the frame transfer to the storage node in the pixel. this means that it also defines the end of the integration time. it is also expressed as a the number of lines - 1. the actual time on which the frame transfer takes place is calculated with the following formula: ft time = (ft_timer-1) * (rot + nr. pixels * clock period) vcal <7:0> this register is the input for the on-chip dac which generates the vcal supply used by the pga. when the register is ?00000000? it sets a vcal of 2.5v. when the register is 1 1111111 then it sets a vcal of 0v. this means that the minimum step you can take with the vcal register is 9.8 mv/bit (2.5v/256bits). vblack <7:0> this register is the input for the on-chip dac which generates the vblack supply used by the pga. when the register is ?00000000? it sets a vblack of 2.5v. when the register is 1 1111111 then it sets a vblack of 0v. this means that the minimum step you can take with the vblack register is 9.8 mv/bit (2.5v/256bits).
noil1sm0300a http://onsemi.com 15 voffset <7:0> this register is the input for the on-chip dac, which generates the voffset supply used by the pga. when the register is ?00000000? it sets a voffset of 2.5v. when the register is 1 1111111 then it sets a vof fset of 0v. this means that the minimum step you can take with the vof fset register is 9.8 mv/bit (2.5v/256bits). ana_in_adc <11:0> this register sets the dif ferent paths that can be used as the adc input (mainly for testing and debugging). the register consists of several ?sub-registers?. sel_test_path (4 bits) these bits select the analog test path of the adc. 0000: no analog test path selected (default) 0001: path of pixel 1 selected 0010: path of pixel 2 selected sel_path (4 bits) these bits select the analog path to the adc. 1111: all paths selected (normal operation) - default 0000: no paths selected (enables adc to be tested through test paths) 0001: path of pixel 1 selected 0010: path of pixel 2 selected bypass_mux (4 bits) these bits enable the possibility to bypass the digital 4 to 1 multiplexer. 0000: no bypass (default) pga_setting <11:0> this register defines all parameters to set the pga. the register consists of different ?sub-registers? gain_pga (4 bits) these bits set the gain of the pga. the following t able 13 gives an overview of the different gain settings. table 13. gain_pga<3.0> gain 0000 1.32 0001 1.56 0010 1.85 0011 2.18 0100 2.58 0101 3.05 0110 3.59 0111 4.22 1000 4.9 1001 5.84 1010 6.84 1011 8.02 1100 9.38 1101 11.2 1110 13.12 1111 15.38 unity_pga (1 bit) this bit sets the pga in unity amplification. 0: no unity amplification, gain settings apply 1: unity gain amplification, gain setting are ignored (default) sel_uni (1 bit) this bit selects whether or not the signal gets a 0.5 amplification before the pga. 0: amplification of 0.5 before pga 1: unity feed through (default) enable_analog_in (1 bit) this bit enables/disables an analog input to the pga. 0: analog input disabled (default) 1: analog input enabled enable_adc (4 bits) these bits can separately enable/disable the different adcs. 0000: no adcs enabled 1111: all adcs enabled (default) 0001: adc 1 enabled 0010: adc 2 enabled sel_calib_fast (1 bit) selects the fast/slow calibration of the adc 0: slow calibration 1: fast calibration
noil1sm0300a http://onsemi.com 16 2adc calibration word <32:0> the calibration word for the adcs is distributed over three registers (13, 14 and 15). these registers all have their default value and changing this value is not recommended. the default register values are: calib_adc<11:0>: 10101101 1111 calib_adc<23:12>: 011011011011 calib_adc<32:24>: 000011011011 data interface (spi) the serial-3-wire interface (or serial-to-parallel interface) uses a serial input to shift the data in the register buffer. when the complete data word is shifted into the register buffer the data word is loaded into the internal register where it is decoded. figure 12. spi schematic the timing of the spi register is explained in the timing diagram below figure 13. timing of the spi spi _clk 20 mhz spi _in b<15> b<14>? b<13>? b<12>? b<11>? b<10>? b<9> b<8> b<7> b<6> b<5> b<4> b<3> b<2> b<1> b<0> dummy b<15> b<14>? b<13> msb---------------- address bits-------------lsb msb--------------------------------------------------------------------------------------- data bits-------------------------------------------------------------------------------- lsb p i_enable upload spi_in (15:12): address bits spi_in (11:0): data bits when spi_enable is asserted the parallel data is loaded into the internal registers of the lupa300. the frequency of spi_clk is 20 mhz or lower. the spi bits have a default value that allows the sensor to be read out at full resolution without uploading the spi bits.
noil1sm0300a http://onsemi.com 17 timing and readout of the image sensor the timing of the sensor consists of two parts. the first part is related with the integration time and the control of the pixel. the second part is related to the readout of the image sensor. integration and readout can be in parallel. in this case, the integration time of frame i is ongoing during readout of frame i-1. figure 14 shows this parallel timing structure. the readout of every frame starts with a frame overhead time (fot) during which the analog value on the pixel diode is transferred to the pixel memory element. after this fot, the sensor is read out line per line. the readout of every line starts with a row overhead time (rot) during which the pixel value is put on the column lines. then the pixels are selected in groups of 4. so in total 160 kernels of 4 pixels are read out. the internal timing is generated by the sequencer. the sequencer can operate in 2 modes: master mode and slave mode. in master mode all the internal timing is controlled by the sequencer, based on the spi settings. in slave mode the integration timing is directly controlled over three pins, the readout timing is still controlled by the sequencer. the selection between master and slave mode is done by the mastermode register of the spi. the sequencer is clocked on the core clock; this is the same clock as the adcs. the core clock is the input clock divided by 4. figure 14. global readout timing readout lines integration frame i+1 integration frame i+2 readout frame i readout frame i+1 fot l1 l2 l480 ... rot k1 k2 k160 ... readout pixels integration timing in mastermode in mastermode the integration time, the dual slope (ds) integration time, and triple slope (ts) integration time are set by the spi settings. figure 15 shows the integration timing and the relationship with the spi registers. the timing concerning integration is expressed in number of lines read out. the timing is controlled by four spi registers which need to be uploaded with the desired number of lines. this number is then compared with the line counter that keeps track of the number of lines that is read out. res1_length <11:0>: the number of lines read out (minus 1) after which the pixel reset drops and the integration starts. res2_timer <11:0>: the number of lines read out (minus 1) after which the dual slope reset pulse is given. the length of the pulse is given by the formula: 4*(12*(gran<1:0>+1)+1) (in clock cycles). res3_timer < 11:0>: the number of lines read out (minus 1) after which the triple slope reset pulse is given. the length of the pulse is given by the formula: 4*(12*(gran<1:0>+1)+1) (in clock cycles). ft_timer <1 1:0>: the number of lines read out (minus 1) after which the frame transfer (ft) and the fot starts. the length of the pulse is given by the formula: 4*(12*(gran<1:0>+1)+1) (in clock cycles).
noil1sm0300a http://onsemi.com 18 figure 15. integration timing in master mode reset_n reset pixel 1 res1_length res2_timer res3_timer ft_timer 1 fot res1_length pixel sample # lines readout the line counter starts with the value 1 immediately after the rising edge of reset_n and after the end of the fot. this means that the four integration timing registers must be uploaded with the desired number of lines plus one. in subsampling mode, the line counter increases with steps of two. in this mode, the counter starts with the value ?2? immediately with the rising edge of reset_n. this means that for correct operation, the four integration timing registers can only be uploaded with an even number of lines if subsampling is enabled. the length of the integration time, the ds integration time and the ts integration time are indicated by 3 output pins: int_time_1, int_time_2 and int_time_3. these outputs are high during the actual integration time. this is from the falling edge of the corresponding reset pulse to the falling edge of the internal pixel sample. figure 16 illustrates this. the internal pixel sample rises at the moment defined by ft_timer (see figure 15) and the length of the pulse is 4*(12*(gran<1:0>+1)+2). figure 16. int_time timing reset_n reset reset ds reset ts int_time1 int_time2 int_time3 (internal ) total integration time ds integration time ts integration time frame transfer
noil1sm0300a http://onsemi.com 19 readout time smaller than or equal to integration time in this situation the res_length register can be uploaded with the smallest possible value, this is the value ?2?. the frame rate is determined by the integration time. the readout time is equal to the integration time, the ft_timer register is uploaded with a value equal to the window size to readout plus one. in case the readout time is smaller than the integration time the ft_timer register is uploaded with a value bigger than the window size. figure 17 shows this principle. while the sensor is being readout the frame_valid signal goes high to indicate the time needed to read out the sensor. when windowing in y direction is desired in this mode (longer integration time than read out time) the following parameters should be set: the integration time is set by the ft_timer register. the actual windowing in y is achieved when the surrounding system discards the lines which are not desired for the selected window. figure 17. readout time smaller than integration time frame_valid total integration time ft_timer fot fot readout pixel reset readout time larger than integration time in case the readout time is larger than then integration time, the res_length register needs to be uploaded with a value larger than two to compensate for the larger readout time. the ft_timer register must be set to the desired window size (in y). only the res_length register needs to be changed during operation. figure 18 shows this example. figure 18. readout time larger than integration time frame_ valid integration time ft_timer fot fot readout pixel reset integration timing in slave mode in slave mode, the registers res_length, ds_timer, ts_timer, and ft_timer are ignored. the integration timing is now controlled by the pins int_time_1, int_time_2 and int_time_3, which are now active low input pins. the relationship between the input pins and the integration timing is illustrated in figure 19. the pixel is reset as soon as in_time_1 is low (active) and int_time_2 and int_time_3 are high. the integration starts when int_time_1 becomes high again and during this integration additional (lower) reset can be given by activating int_time_2 and int_time_3 separately. at the end of the desired integration time the frame transfer starts by making all 3 int_time pins active low simultaneously. there is always a small delay between the applied external signals and the actual internally generated pulses. these delays are also shown in figure 19. in case non destructive readout is used, the pulses on the input pins still need to be given. by setting the ndr bit to ?1? the internal pixel reset pulses are suppressed but the external pulses are still needed to have the correct timing of the frame transfer.
noil1sm0300a http://onsemi.com 20 figure 19. integration timing in slave mode int_time_1 int_time_2 ds reset (internal) ts reset (internal) pixel sample (internal) total integration time ds integration time ts integration time spi reset_n int_time_3 fot fot simultanious min 12 clk periods min 12 clk periods reset (internal) readout timing the sensor is readout row by row. the line_valid signal shows when valid data of a row is at the outputs. frame_valid shows which line_valids are valid. line_valids when frame_valid is low, must be discarded. figure 20 and figure 21 illustrate this. note: the frame_valid signal automatically goes low after 480 line_valid pulses in mastermode. figure 20. line_valid timing 12.5ns valid validvalid valid valid valid clk invalid data <9:0> line_valid invalid?invalid figure 21. frame_valid timing frame_valid line_valid
noil1sm0300a http://onsemi.com 21 the data at the output of the sensor is clocked on the rising edge of clk. there is a delay of 3.2 ns between the rising edge of clk and a change in data<9:0>. after this delay data<9:0> needs 6 ns to become stable within 10% of vddd. this means that data<9:0> is stable for a time equal to the clock period minus 6 ns. figure 22 illustrates this. note: in slave mode, line valids that occur beyond the desired image window should be discarded by the user?s image data acquisition system figure 22. data<9.0> valid timing data <9:0> invalid clk valid invalid? invalid valid line_valid 4ns 3.2 + 6ns clk period - 6ns 3.2ns 6ns readout timing in slave mode the start pointer of the window to readout is determined by the start_x and start_y registers (as by readout in master mode). the size of the window in x-direction is also determined by the nb_of_pix register. the length of the window in y-direction is determined by the externally applied integration timing. the sensor does not know the desired y-size to readout. it therefore reads out all lines starting from start_y. the readout of lines continues until the user decides to start the fot. even when the line pointer wants to address non existing rows (row 481 and higher), the sequencer continues to run in normal readout mode. this means that frame_valid remains high and line_valid is toggled as if normal lines are readout. the controller should take care of this and ignore the line_valids that correspond with non existing lines and line_valids that correspond with lines that are not inside the desired readout window. the length of the fot and rot is still controlled by the gran register as described in this data sheet. readout time longer than integration time the sensor should be timed according to the formulas and diagram here: 1. int_time_1 should be brought high at time (read_t - int_t) and preferably immediately after the falling edge of line_valid. 2. at time read_t all int_time_x should simultaneous go low to start the fot. this is immediately after the falling edge of the last line_valid of the desired readout window. fot readout fot int_time1 reset integration readout time shorter than integration time the sensor should be timed according to the formulas and diagram here: 1. int_time_1 should be brought high after a minimum 2 s reset time and preferably immediately after the falling edge of the first line_valid. 2. at time read_t after the last valid line_valid of the desired window size, all other line_valids should be ignored. 3. after the desired integration length all int_time_x should simultaneous go low to start the fot. fot readout fot int_time1 reset integration dummy line_valids
noil1sm0300a http://onsemi.com 22 startup timing on startup, vddd should rise together with or before the other supplies. the rise of vddd should be limited to 1v/100 s to avoid activation of the on chip esd protection circuitry. during the rise of vddd an on chip por_n signal is generated that resets the spi registers to its default setting. after vddd is stable the spi settings can be uploaded to configure the sensor for future readout and light integration. when powering on the vddd supply, the reset_n pin should be kept low to reset the on chip sequencer and addressing logic. the reset_n pin must remain low until all initial spi settings are uploaded. reset_n pin must remain low for at least 500 ns after all supplies are stable. the rising edge of reset_n starts the on chip clock division. the second rising edge of clk after the rising edge of reset_n, triggers the rising edge of the core clock. some spi settings can be uploaded after the core clock has started. figure 23. startup timing power on?vddd stable spi upload min 500ns spi upload if required invalid invalid spi upload vddd power supply core clock (internal) system clock (external) reset_n por_n (internal) sequencer reset timing by bringing reset_n low for at least 50 ns, the on chip sequencer is reset to its initial state. the internal clock division is restarted. the second rising edge of clk after the rising edge of reset_n the internal clock is restarted. the spi settings are not affected by reset_n. if needed the spi settings can be changed during a low level of reset_n. figure 24. sequencer reset timing system (internal) normal operation normal operation invalid min 50 ns clock (external) reset_n core clock (internal) sync_y (internal) clock_y
noil1sm0300a http://onsemi.com 23 pin list table 14. pinlist pin no. name type description 1 gnd adc ground ground supply of the adcs 2 data<5> output databit<5> 3 data<6> output databit<6> 4 data<7> output databit<7> 5 data<8> output databit<8> 6 data<9> output databit<9> (msb) 7 gnd d ground digital ground supply 8 v ddd supply digital power supply (2.5v) 9 gnd adc ground ground supply of the adcs 10 v adc supply power supply of the adcs (2.5v) 11 gnd a ground ground supply of analog readout circuitry 12 v dda supply power supply of analog readout circuitry (2.5v) 13 adc_bias biasing biasing of adcs. connect with 10 k to vadc and decouple with 100n to gnd_adc 14 bias4 biasing biasing of amplifier stage. connect with 110 k to vdda and de- couple with 100 nf to gnda 15 bias3 biasing biasing of columns. connect with 42 k to vdda and decouple with 100 nf to gnda 16 bias2 biasing biasing of columns. connect with 1.5 m to vdda and decouple with 100 nf to gnda. 17 bias1 biasing biasing of imager core. connect with 500 k to vdda and decouple with 100 nf to gnda 18 vpix supply power supply of pixel array (2.5v) 19 spi_enable digital input enable of the spi 20 spi_clk digital input clock of the spi. (max. 20 mhz) 21 spi_data digital i/o data line of the spi. bidirectional pin 22 vmem_h supply supply of vmem_high of pixelarray (3.3v) 23 gnd_drivers ground ground of pixel array drivers 24 vreset_1 supply reset supply voltage (typical 3.3v) 25 vreset_2 supply dual slope reset supply voltage. connect to other supply or ground when dual slope reset is not used 26 vreset_3 supply triple slope reset supply voltage. connect to other supply or ground when triple slope reset is not used 27 precharge_bias bias connect with 68 k to vpix and decouple with 100 nf to gnd_drivers 28 line_valid digital output indicates when valid data is at the outputs. active high 29 frame_valid digital output indicates when valid frame is readout 30 int_time_3 digital i/o in master mode: output to indicate the triple slope integration time. in slave mode: input to control the triple slope integration time 31 int_time_2 digital i/o in master mode: output to indicate the dual slope integration time. in slave mode: input to control the dual slope integration time 32 int_time_1 digital i/o in master mode: output to indicate the integration time in slave mode: input to control integration time 33 v ddd supply digital power supply (2.5v)
noil1sm0300a http://onsemi.com 24 table 14. pinlist pin no. description type name 34 gnd d ground digital ground supply 35 v dda supply power supply of analog readout circuitry (2.5v) 36 gnd a ground ground supply of analog readout circuitry 37 reset_n digital input sequencer reset, active low 38 clk digital input readout clock (80 mhz), sine or square clock 39 v adc supply power supply of the adcs (2.5v) 40 gnd adc ground ground supply of the adcs 41 v ddo supply power supply of the output drivers (2.5v) 42 gnd o ground ground supply of the output drivers 43 data<0> output databit<0> (lsb) 44 data<1> output databit<1> 45 data<2> output databit<2> 46 data<3> output databit<3> 47 data<4> output databit<4> 48 v adc supply power supply of the adcs (2.5v)
noil1sm0300a http://onsemi.com 25 package drawing figure 25. package drawing (001 ? 45394)
noil1sm0300a http://onsemi.com 26 mechanical package specification mechanical specifications min typ max units die (with pin 1 to the left center) die thickness ? 0.01 0.74 0.01 mm die center, x offset to the center of the package ? 50 0 50 m die center, y offset to the center of the package ? 50 0 50 m die position, x tilt ? 1 0 1 deg die position, y tilt ? 1 0 1 deg die placement accuracy in package ? 50 50 m die rotation accuracy ? 1 1 deg optical center referenced from package center (x ? dir) 6.1 mm optical center referenced from package center (y ? dir) 7.1 mm distance from pcb plane to top of the die surface 1.25 mm distance from top of the die surface to top of the glass lid 1 mm glass lid thickness 0.6 mm spectral range for window 400 1000 nm transmission of the glass lid 92 % mechanical shock jesd22 ? b104c; condition g 2000 g vibration jesd22 ? b103b; condition 1 20 2000 hz mounting profile lead ? free infra ? red (ir) profile for lcc package if no socket is used
noil1sm0300a http://onsemi.com 27 glass lid the lupa300 image sensor uses a glass lid without any coatings. figure 26 shows the transmission characteristics of the glass lid. as shown in figure 26, no infrared attenuating filter glass is used. (source: http://www.pgo ? online.com). figure 26. transmission characteristics of the glass lid handling precautions for proper handling and storage conditions, refer to the on semiconductor application note an52561. limited warranty on semiconductor?s image sensor business unit warrants that the image sensor products to be delivered hereunder, if properly used and serviced, will conform to seller?s published specifications and will be free from defects in material and workmanship for two (2) years following the date of shipment. if a defect were to manifest itself within 2 (two) years period from the sale date, on semiconductor will either replace the product or give credit for the product. return material authorization (rma) on semiconductor packages all of its image sensor products in a clean room environment under strict handling procedures and ships all image sensor products in esd-safe, clean-room- approved shipping containers. products returned to on semiconductor for failure analysis should be handled under these same conditions and packed in its original packing materials, or the customer may be liable for the product. acceptance criteria specification the product acceptance criteria is available on request. this document contains the criteria to which the lupa300 is tested before being shipped. ordering code information n on semiconductor designator l1 = lupa image sensors opto m = mono e = color micro lens standard process functionality placeholder i oc commercial temp range d = glass w = windowless resolution: 0.3 megapixel l1 s m q = lcc w = wafer sales q 0300 a ? d
noil1sm0300a http://onsemi.com 28 acronyms acronym description adc analog-to-digital converter afe analog front end bl black pixel data cdm charged device model cds correlated double sampling cmos complementary metal oxide semiconductor crc cyclic redundancy check dac digital-to-analog converter ddr double data rate dft design for test dnl differential nonlinearity ds double sampling dsnu dark signal nonuniformity eia electronic industries alliance esd electrostatic discharge fe frame end ff fill factor fot frame overhead time fpga field programmable gate array fpn fixed pattern noise fps frames per second fs frame start hbm human body model img regular pixel data inl integral nonlinearity acronym description ip intellectual property le line end ls line start lsb least significant bit lvds low-voltage differential signaling mbs mixed boundary scan msb most significant bit pga programmable gain amplifier pls parasitic light sensitivity prbs pseudo-random binary sequence prnu pixel random nonuniformity qe quantum efficiency rgb red green blue rma return material authorization rms root mean square roi region of interest rot row overhead time s/h sample and hold snr signal-to-noise ratio spi serial peripheral interface tbd to be determined tia telecommunications industry association t j junction temperature tr training pattern % rh percent relative humidity
noil1sm0300a http://onsemi.com 29 glossary conversion gain a constant that converts the number of electrons collected by a pixel into the voltage swing of the pixel. con- version gain = q/c where q is the charge of an electron (1.602e 19 coulomb) and c is the capacitance of the photodiode or sense node. cds correlated double sampling. this is a method for sampling a pixel where the pixel voltage after reset is sampled and subtracted from the voltage after exposure to light. dnl differential nonlinearity (for adcs) dsnu dark signal nonuniformity. this parameter characterizes the degree of nonuniformity in dark leakage currents, which can be a major source of fixed pattern noise. fill-factor a parameter that characterizes the optically active percentage of a pixel. in theory, it is the ratio of the actual qe of a pixel divided by the qe of a photodiode of equal area. in practice, it is never measured. inl integral nonlinearity (for adcs) ir infrared. ir light has wavelengths in the approximate range 750 nm to 1 mm. lux photometric unit of luminance (at 550 nm, 1lux = 1 lumen/m 2 = 1/683 w/m 2 ) pixel noise variation of pixel signals within a region of interest (roi). the roi typically is a rectangular portion of the pixe l array and may be limited to a single color plane. photometric units units for light measurement that take into account human physiology. pls parasitic light sensitivity. parasitic discharge of sampled information in pixels that have storage nodes. prnu photo-response nonuniformity. this parameter characterizes the spread in response of pixels, which is a source of fpn under illumination. qe quantum efficiency. this parameter characterizes the effectiveness of a pixel in capturing photons and con- verting them into electrons. it is photon wavelength and pixel color dependent. read noise noise associated with all circuitry that measures and converts the voltage on a sense node or photodiode into an output signal. reset the process by which a pixel photodiode or sense node is cleared of electrons. ?soft? reset occurs when the reset transistor is operated below the threshold. ?hard? reset occurs when the reset transistor is operated above threshold. reset noise noise due to variation in the reset level of a pixel. in 3t pixel designs, this noise has a component (in units of volts) proportionality constant depending on how the pixel is reset (such as hard and soft). in 4t pixel designs, reset noise can be removed with cds. responsivity the standard measure of photodiode performance (regardless of whether it is in an imager or not). units are typically a/w and are dependent on the incident light wavelength. note that responsivity and sensitivity are used interchangeably in image sensor characterization literature so it is best to check the units. roi region of interest. the area within a pixel array chosen to characterize noise, signal, crosstalk, and so on. the roi can be the entire array or a small subsection; it can be confined to a single color plane. sense node in 4t pixel designs, a capacitor used to convert charge into voltage. in 3t pixel designs it is the photodiode itself. sensitivity a measure of pixel performance that characterizes the rise of the photodiode or sense node signal in volts upon illumination with light. units are typically v/(w/m 2 )/sec and are dependent on the incident light wavelength. sensitivity measurements are often taken with 550 nm incident light. at this wavelength, 1 683 lux is equal to 1 w/m 2 ; the units of sensitivity are quoted in v/lux/sec. note that responsivity and sensitivity are used interchangeably in image sensor characterization literature so it is best to check the units. spectral response the photon wavelength dependence of sensitivity or responsivity. snr signal-to-noise ratio. this number characterizes the ratio of the fundamental signal to the noise spectrum up to half the nyquist frequency. temporal noise noise that varies from frame to frame. in a video stream, temporal noise is visible as twinkling pixels.
noil1sm0300a http://onsemi.com 30 appendix a: frequently asked questions q: how does the dual (multiple) slope extended dynamic range mode work? a: the green lines are the analog signal on the photodiode, which decrease as a result of exposure. the slope is determined by the amount of light at each pixel (the more light the steeper the slope). when the pixels reach the saturation level the analog signal does not change despite further exposure. as shown, without any double slope pulse pixels p3 and p4 reaches saturation before the sample moment of the analog values; no signal is acquired without double slope. when double slope is enabled a second reset pulse is given (blue line) at a certain time before the end of the integration time. this double slope reset pulse resets the analog signal of the pixels below this level to the reset level. after the reset the analog signal starts to decrease with the same slope as before the double slope reset pulse. if the double slope reset pulse is placed at the end of the inte gration time (90% for instance) the analog signal that reach the saturation levels are not saturated anymore (this increases the optical dynamic range) at read out. it is important to note that pixel signals above the double slope reset level are not influenced by this double slope reset pulse (p1 and p2). if desired, additional reset pulses can be given at lower levels to achieve multiple slope. figure 27. dual slope diagram p4 p3 p2 p1 reset level 1 reset level 2 saturation level total integration time reset pulse double slope reset pulse read out double slope reset time (usually 5- 10% of the total integration time) on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 noil1sm0300a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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